1. Field of Invention
This invention relates to the general construction of Bipolar Transistors with innovative device concept of the depleted emitter region for the reduction of charge region between emitter to the base. This invention also discloses various bipolar transistor device structures with depleted emitter for the improvement of the transistor speed.
2. Description of the Related Art
U.S. Pat. No. 4,259,680 Lepselter and Sze disclosed a bipolar transistor structure for a N+PN+ transistor for a high speed lateral bipolar transistor, U.S. Pat. No. 4,483,726 Issac et al disclosed a double self-aligned fabrication process for making a bipolar transistor structure having a small polysilicon to extrinsic base contact area, U.S. Pat. No. 4,581,319 Wieder et al disclosed the method for the manufacturing of bipolar transistor structures with self adjusting emitter and base regions for the extreme high frequency circuits. U.S. Pat. No. 4,729,965 Tamaki et al disclosed the method of forming extrinsic base by diffusion from polysilicon/silicide source and emitter by lithography. U.S. Pat. No. 5,024,957 Harame et al disclosed a method of fabricating a bipolar transistor with ultra-thin epitaxial base. U.S. Pat. No. 5,098,854 Kapoor et al disclosed the process for forming self aligned silicide base contact for bipolar transistor. U.S. Pat. No. 5,101,256 Harame et al disclosed a bipolar transistor with ultra thin epitazial base and method of fabricating same. All above patent disclosures are using heavily doped n or p as the emitter.